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Status report on fast serial link, 28 Feb 2001


This document describes the current design and status of the communication interface card intended for use with a new CUO array controller. The proposal was to provide a replacement for the existing board which would improve the performance, throughput, with state of the art components. The board consists of a serial duplex fibre interface, a first-in- first-out (FIFO), control logic and a PCI-bus controller. It was originally considered making a board that would be a direct replacement of the exiting interface card, i.e. retain an identical serial protocol, and to have the ability to up-grade/convert to a faster transmission rate when a new controller arrives, though this was dropped, after discussions between myself and Preben, as a unnecessary waste of resources and time.

Design Description

It was decided at the beginning to retain the duplex fibre optic link using the same multi-mode fibre as used on the existing boards. Preben proposed the PCI bus and the Cypress HotLink CY7B9x3 transmitter/receiver chipset, which have been adopted. Suitable fibre optical transmitter and receiver modules from Hewlett Packard (HFBR-x119T) have been selected. The CY7B9x3 chips' internal encoding and decoding (8B/10B) will be used. Note, it is known that Cypress has since brought out a new combined transmitter/ receiver single chip, the CY7C924DX, and this can be used to replace the separate devices currently been used.

An important decision was to use the industrial standard PCI bus, now found in all personal computers. This bus is relatively complicated and so a proprietary interface device has been selected. The AMCC "Matchmaker" S5933 was chosen. This chip converts the PCI bus to a much simpler local bus with four definable `Pass-Thru' data channels. Internal 32-bit wide, 8 deep FIFO channels have been selected for both directions, for communicating to the PCI bus. The S5933 can act as a bus master. A software Linux driver has been procured for the AMCC controller from Sheldon Instruments. This driver package comes with working examples and full source code.

Another important criteria is that the data flow from the array being read is continuous. This is arranged on the existing board with a full frame buffer. The buffer has been replaced in this new design by a first-in- first-out (FIFO) memory. This option can be used because the PCI bus can easily sustain the maximum possible pixel arrival rate from the array. Modern PCs will have no problems handling the data in real-time, especially since the AMCC controller chip can initiate bus transfers, and it was considered to duplicate PC memory on the board would only increase its complexity, so compromise its reliability. Cypress asynchronous CY7C46xA devices have been chosen for the FIFO and will make up a 32-bit wide memory. The system has been configured so that as soon as the first location in memory is full a transfer is initiated.

All the `glue-logic' is implemented with an Altera MAX7000 PLD, the same family of devices already used in Copenhagen. This device will include a state-machine to ensure priority is given to data transfer from the array. The Cypress HOTLink devices work with bytes but to get the maximum throughput from the PCI bus all communication over the bus will be 32 bits. The conversion between long words and bytes is handled by the PLD.

To assist in the development a developer's kit was purchased from AMCC. This kit includes a board with the Matchmaker chip and prototyping area. The first prototype interface board will be built with this developer's kit.

Design Status

The status of the design is that all the hardware components have been acquired, we have the AMCC developer's kit and the PCI driver package. Preliminary code has been written for the PLD, and simulated up to a data transfer rate of 240 MHz, and work has started on the construction of the board. Also a home-made prototype board has been made to test out various ideas before putting them on to the actual AMCC board. The home-made board is only waiting for the PLD to be programmed and the chips to be plugged in. Later this board will be used to emulate the array controller. Once everything is found to be satisfactory on the home-made board the design will be finished off on the AMCC board.

At the end of March 2001 a student will be arriving at the NOT, for some industrial training, and he will work on the AMCC control interface. No work has yet been done with the PCI driver.

There is little additional information I need from CUO-IJAF for the technical development, though obviously we need to agree on the clock frequency. If we move to the new Cypress CY7C924DX device then the maximum frequency can only be 200 MHz, where I've verified my design at 240 MHz, (and 200 MHz). Most of the important definitions are handled by the software and the driver. The board only accepts data on the incoming channel and passes it on, and similarly transmits commands as they arrive on the PCI bus from the control program. The length of the commands needs to be clarified, though the board is designed to take byte, word or long word lengths.

Below is an estimate of the time required to complete the first prototype board. In addition to this time there is the software control development. This area is not my speciality and help would be advantageous. A simple driver needs to be written to test the board and hopefully this can be done in a few weeks. Designing a printed circuit board (PCB) will take some time since it includes the learning of the design package. It is thought that some of this work could be done by Carlos Perez. It must be noted that the times given are assuming full time work which can not be the case since obviously the telescope takes precedence, and there are other projects to work on as well involving the telescope directly.


Graham Cox 28 Feb 2001.

Figure 2:   PCI card, block diagram

next up previous contents
Next: About this document Up: AiC Report to NOT Previous: Measurements of M1 dynamics

Tim Abbott, AiC
Wed Mar 21 12:56:05 GMT 2001

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